This invention relates to an extended storage system for a data processing system, and particularly to an extended storage system suited to transfer data between hierarchical storages and an extended storage.
U.S. Pat. No. 4,476,524 issued to D. T. Braun et al. on Oct. 9, 1984, discloses a data processing system which includes a data transfer path between a main storage (termed MS hereinafter) and an extended storage, termed ES hereinafter (or page storage) and performs data transfer between the MS and extended storage using the data transfer path.
An earlier system for improving the adjustment of difference in the operating speed between a processor and MS in a data processing system may be found in Japanese patent application JP-A-52-71138 (corresponding to JP-B-57-57782). This document discloses hierarchical storages in which a small-capacity, high-speed high ranking storage, e.g., a buffer storage (termed BS hereinafter) is provided on the part of the processor, and an intermediate-rank storage, e.g., a work storage (termed WS hereinafter) serving as a second-rank buffer, having an intermediate speed and intermediate capacity as compared to the BS and MS is provided between the BS and MS. In this case, the MS is the lowest-rank storage.
U.S. Pat. No. 4,639,862, issued to H. Wada on Jan. 27, 1987, discloses an addressing system for extended storage. The contents of the above publication are introduced merely as a background to the present patent application.
In reading out data, such as an instructions or operand, stored in three or more hierarchical storages, the data is read out from a storage of as high rank as possible which holds the object data or contains a copy of the data. Only if any storage higher in rank than MS does not contain a copy of data, is it read out from the MS. Control is made to place frequently used data of at a higher rank storage. The processing speed is thus enhanced.
In writing data into hierarchical storages, data in storages of all ranks are not rewritten at once, but instead, altered data is rewritten in a store-in manner for storages below a certain rank. The processing speed is thus enhanced.
Among control modes of rewriting data in a storage of a certain rank, rewriting data immediately, after rewriting data in the certain rank storage, to the next lower ranking storage is categorized to be "store-through" or "write-through" mode, while rewriting data by returning the data to the next lower ranking storage when the rewrited data in the active storage is no longer used is categorized to be "store-in" or "write-back" mode. In a hierarchical storage system which controls storing into an intermediate storage in store-in mode, the MS which is the lowest-rank storage does not necessarily have its data always updated to the newest state.
Recent advanced semiconductor technologies have provided higher operating speeds for processors, year after year, whereas MSs have achieved relatively little progress in the operating speed, although capacities have increased and their costs lowered. Therefore, the difference of speed between these devices is further increasing.
In the data processing system disclosed in the above-mentioned U.S. Pat. No. 4,476,524, central processors (CPs) and channel processors (CHs) are connected through a system controller (SC) to main storages (MSs), which are connected with page storages (PSs) through an MS/PS data bus.